Verification progress tracking with obsidian Dec 5, 2022 The main question in verification is “Are we done yet?” And before you mutter something about covergroups and code coverage and turn back to funny Untangling Virtual Methods Oct 22, 2022 I’m one of those weird guys who from time to time write answers on r/systemverilog. One day I saw there a rather simple question from my point of Statics in SystemVerilog Oct 2, 2022 This is a translation of my original post on FPGA-Systems, an awesome Russian-speaking community for everything FPGA. There may be some confusion